General · GitHub ·5 ★

SPI-Slave-with-RAM-UVM

This project uses UVM to verify an SPI Slave connected to internal RAM. It includes multiple agents (active and passive) and integrates assertion-based verifica

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Details

Owner: MohamedHussein27
Category: General
Platform: GitHub
Framework: custom
Language: systemverilog
Stars: 5
First indexed: 2026-04-16
Last active: 2025-05-05
Directory sync: 2026-04-16
Source URL: https://github.com/MohamedHussein27/SPI-Slave-with-RAM-UVM

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